Espressif Systems /ESP32-S3 /SENSITIVE /DMA_APBPERI_LC_PMS_CONSTRAIN_1

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Interpret as DMA_APBPERI_LC_PMS_CONSTRAIN_1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 0DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 0DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 0DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 0DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 0DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1

Description

lc dma permission configuration register 1.

Fields

DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0

lc’s permission(store,load) in data region0 of SRAM

DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1

lc’s permission(store,load) in data region1 of SRAM

DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2

lc’s permission(store,load) in data region2 of SRAM

DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3

lc’s permission(store,load) in data region3 of SRAM

DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0

lc’s permission(store,load) in dcache data sram block0

DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1

lc’s permission(store,load) in dcache data sram block1

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